1. Field of the Invention
The present invention relates to a dynamic random access memory (DRAM) structure. More particularly, the present invention relates to a vertical DRAM structure.
2. Description of the Related Art
As the level of integration of semiconductor devices increases, dimensions of circuit devices must be reduced according to design rules. Theoretically, line width of gates can be reduced ad infinitum. In practice, however, line width is limited by the resolution in photolithographic operations as well as length of device channel. Since a source/drain region is formed using the gate line as an ion mask in an ion implantation, line width of the gate is almost equivalent to length of the channel. Although the reduction of channel length is able to increase drifting speed of carriers from one source/drain terminal to the next, the hot carrier effect will intensify resulting in a higher rate of device failure. Hence, an upper limit is set on the possible level of integration for conventional DRAM devices.